The present invention generally relates to horizontal scanning frequency multiplying circuits, and more particularly to a horizontal scanning frequency multiplying circuit which synchronizes with the phase of a horizontal synchronizing signal within a composite synchronizing signal to obtain a signal having a frequency which is a multiple of the horizontal scanning frequency, and has a circuit construction which facilitates the circuit to be manufactured in the form of an integrated circuit (IC).
Generally, when recording an address signal of a pulse-code-modulated (PCM) signal format onto a rotary recording medium together with a video signal, this address signal is recorded within a horizontal blanking period having a predetermined order (predetermined positional relationship) from a starting position of each field of the video signal. In addition, when broadcasting a signal in which a signal for displaying characters is multiplexed with the video signal, for example, the PCM signal describing the characters is inserted within the horizontal blanking period of the video signal. When recording, reproducing, or transmitting the video signal inserted with the above kind of a PCM signal, it becomes necessary to obtain a signal having a frequency which is a multiple of the horizontal scanning frequency. Accordingly, a horizontal scanning frequency multiplying circuit is used.
The conventional horizontal scanning frequency multiplying circuit had the following circuit construction. That is, a composite synchronizing signal is supplied to a first monostable multivibrator wherein the composite synchronizing signal is converted into a pulse series having a pulse width corresponding to a distance between the rise (or fall) in the horizontal synchronizing signal within the composite synchronizing signal and a position approximately 3H/4 (H indicates one horizontal scanning period) from that rise (or fall) in the horizontal synchronizing signal, and having a repetition frequency equal to the horizontal scanning frequency. This pulse series thus obtained is supplied to a second monostable multivibrator, from which another pulse series having a horizontal scanning frequency f.sub.H is obtained. This pulse series obtained from the second monostable multivibrator does not respond to an equalizing pulse or a vertical synchronizing signal within the input composite synchronizing signal, and responds only to the horizontal synchronizing signal. The above pulse series of the frequency f.sub.H is supplied to a phase-locked-loop (PLL). The PLL comprises a voltage controlled oscillator (VCO) which oscillates at a frequency Nf.sub.H (N is an integer), a frequency divider for frequency-dividing an output oscillation frequency of the VCO, and a phase comparator for comparing phases of the output of the second monostable multivibrator and an output of the frequency divider, to supply an output error signal to the VCO and control the oscillation frequency of the VCO. A signal having a frequency Nf.sub.H which is N times the horizontal scanning frequency f.sub.H, is accordingly obtained from the VCO.
However, the monostable multivibrator generally comprises a capacitor and a trimming variable resistor for finely adjusting the time constant. Hence, if the above described circuit as a whole is manufactured in the form of an integrated circuit, these capacitor and variable resistor must be provided exterior to the integrated circuit. This means that the number of pins of the integrated circuit is increased. Accordingly, the conventional horizontal scanning frequency multiplying circuit had a disadvantage in that it was not suited to be manufactured in the form of an integrated circuit. Furthermore, since the above fine adjustment must be performed during the manufacturing process, the productivity decreased.